1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device which senses data by comparing a data potential with reference potentials.
2. Description of the Related Art
In semiconductor memory devices such as a DRAM (dynamic random access memory), a flash memory, and a ferroelectric memory, generally, a potential of read data is compared with a predetermined reference potential to perform the sensing of data. The sense amplifier that performs the sensing of data needs to accurately detect HIGH data and LOW data that are read from a memory core. There is thus a need for the provision of a proper reference potential.
FIG. 1 is a drawing showing an example of the construction of a related-art semiconductor memory device. The semiconductor memory device of FIG. 1 is illustrated by taking a ferroelectric memory as an example, and is provided with two sense amplifiers for the purpose of sensing data from 1T1C-type memory cells. One sense amplifier compares a data potential with a HIGH reference potential, and the other sense amplifier compares the data potential with a LOW reference potential.
The semiconductor memory device of FIG. 1 includes an address buffer 10, pre-sense amplifiers 11-0 and 11-1 for reference cells, pre-sense amplifiers 12-0 through 12-n for memory cells, a sense amplifier 13 for reference cells, sense amplifiers 14-0 through 14-n and 15-0 through 15-n for memory cells, an output buffer 16, reference cells R00 through R11, and memory cells C00 through Cn1.
Each of the memory cells and the reference cells is comprised of a ferroelectric capacitor and an access transistor. Word lines WL0 and WL1 are connected to the gate of the access transistors. For the sake of simplicity, only two word lines are illustrated with respect to two rows of memory cells. In actuality, however, a number of word lines may be arranged with respect to a number of memory cell rows. The address buffer 10 selectively activates a word line corresponding to an input address, thereby making access transistors conductive, resulting in one end of ferroelectric capacitors being coupled to bit lines/BLR and BLR and BL0 through BLn. The other end of the ferroelectric capacitors is connected to either a plate line CP0 or a plate line CP1.
A positive or negative voltage is applied to a ferroelectric capacitor to cause polarization, thereby performing data writing. The presence/absence of a polarization reversal current in responses to a positive potential applied to the ferroelectric capacitor is detected, thereby performing data reading. In data writing, the word line WL is selected (HIGH) to make corresponding access transistors conductive. When a positive or negative voltage is applied between a bit line and a plate line, this voltage is applied to a ferroelectric capacitor, resulting in specified data being written. In data reading, a word line is selected to make corresponding access transistors conductive, and a plate line is set to a power supply potential. As a result of this operation, electric charge in amounts corresponding to the data stored in a ferroelectric capacitor moves to a bit line. The current caused by the movement of electric charge is sensed and converted into a voltage signal by the pre-sense amplifiers 11-0 and 11-1 and 12-0 through 12-n. 
The sense amplifier 13 for reference cells compares a LOW potential read from a reference cell with a HIGH potential read from another reference cell for amplification of a potential difference. With this, a LOW reference potential Lref and a HIGH reference potential Href are generated.
FIGS. 2A and 2B are drawings showing signal waveforms indicative of the operation of sense amplifiers for memory cells. The HIGH reference potential Href illustrated by solid lines and a data potential illustrated by dotted lines are compared with each other by a latch-type sense amplifier (one of 14-0 through 14-n) as indicated as “SENSING BY LSA”. Further, the LOW reference potential Lref illustrated by solid lines and the data potential illustrated by dotted lines are compared with each other by a latch-type sense amplifier (one of 15-0 through 15-n) as indicated as “SENSING BY RSA”.
FIG. 2A shows signal waveforms indicative of a sense amplifier operation when a data potential read from a memory cell is HIGH. In this case, sensing by LSA has difficulty amplifying a difference of input potentials because the two input potentials for comparison are substantially equal or have little difference. Sensing by RSA, on the other hand, properly amplifies a difference of input potentials because the two input potentials for comparison have a sufficient difference that is required for latching operation. As a result, the data potential shown by dotted lines becomes HIGH while the LOW reference potential Lref shown by solid lines becomes LOW. Since the data potential is pulled toward HIGH, the potential Href becomes LOW in the sensing operation by LSA.
FIG. 2B shows signal waveforms indicative of a sense amplifier operation when a data potential read from a memory cell is LOW. In this case, sensing by RSA has difficulty amplifying a difference of input potentials because the two input potentials for comparison are substantially equal or have little difference. Sensing by LSA, on the other hand, properly amplifies a difference of input potentials because the two input potentials for comparison have a sufficient difference that is required for latching operation. As a result, the data potential shown by dotted lines becomes LOW while the HIGH reference potential Href shown by solid lines becomes HIGH. Since the data potential is pulled toward LOW, the potential Lref becomes HIGH in the sensing operation by RSA.
In this manner, one of the two sense amplifiers that is given a greater difference of input potentials completes a sensing operation faster and stronger than the other during sense-amplifier amplification. The sense amplifier provided with a smaller difference of input potentials completes its sensing operation by following the operation of the other. Read data sensed by the sensing operation as described above is output to an exterior of the semiconductor memory device through the output buffer 16.
[Patent Document 1] Patent Application Publication No. 2002-157876.
[Patent Document 2] Patent Application Publication No. 2002-133857.
A data potential read from an actual memory cell (or reference cell) conforms to a certain distribution due to process manufacturing variation. FIG. 3 is a diagram showing an example of a data potential distribution. A horizontal axis represents a data potential read from a memory cell, and a vertical axis represents the number of cells that exhibit respective data potentials. Memory cells having data “0” written therein conform to a data potential distribution 20, and memory cells having data “1” written therein conform to a data potential distribution 21. Such data-potential distribution map is obtained by plotting the number of bits of failed cells while changing a reference potential gradually on the horizontal axis.
FIG. 3 illustrates a data potential distribution that provides correct data reading. All the data potentials of memory cells having “0” data that conform to the data potential distribution 20 are distanced farther away from the HIGH reference potential Href than from the LOW reference potential Lref. It follows that sensing operation driven by the reference potential Href becomes predominant, resulting in all the data of memory cells having “0” data being sensed as LOW. Also, all the data potentials of memory cells having “1” data that conform to the data potential distribution 21 are distanced farther away from the LOW reference potential Lref than from the HIGH reference potential Href. It follows that sensing operation driven by the reference potential Lref becomes predominant, resulting in all the data of memory cells having “1” data being sensed as HIGH.
FIG. 4 is a diagram showing a data potential distribution in the case where data reading produces an incorrect result. In FIG. 4, a data potential 22 that belongs to a data potential distribution 20A of memory cells with “0”1 data is positioned at a distance A from the LOW reference potential Lref, which is greater than a distance B from the HIGH reference potential Href. As a result, sensiong operation driven by the reference potential Lref becomes predominant, resulting in the “0”1 data of memory cells having the data potential 22 being sensed as HIGH. As for the memory cells having “1”data that conform to a data potential distribution 21A, all the data potentials are distanced farther away from the LOW reference potential Lref than from the HIGH reference potential Href. It follows that sensing operation driven by the reference potential Lref becomes predominant, resulting in the “1” data of these memory cells being sensed as HIGH.
Accordingly, there is a need for a semiconductor memory device in which data reading is correct regardless of data potential distributions when data sensing is performed by comparing a data potential with a plurality of reference potentials.